This invention relates generally to semiconductor chip device assembly, and in particular to flip chip package construction. More specifically, the invention relates to a method of adding filler material to non-filled or low-filled underfill material between the semiconductor chip and substrate using a highly filled fillet during chip packaging.
In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit (IC) chip or xe2x80x9cdiexe2x80x9d) may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g. wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is xe2x80x9cflippedxe2x80x9d onto its active circuit surface so that the solder balls form electrical connections directly between the chip and conductive traces on a packaging substrate. Semiconductor chips of this type are commonly called xe2x80x9cflip chipsxe2x80x9d.
The initial packaging of the chip occurs in two steps. First, the chip is electrically connected to the substrate and then the chip is mechanically (or adhesively) bonded to the substrate. The chip is electrically bonded to the substrate by applying solder balls to the active circuit surface of the chip. As an example, the solder may be composed of a low melting point eutectic material or a high lead material. Prior to bonding the chip to a substrate, solder flux is applied to either the active surface of the chip or the packaging substrate surface. The flux serves primarily to aid the flow of the solder, such that the solder balls make good contact with traces on the packaging substrate. It may be applied in any of a variety of methods, including brushing or spraying, or dipping the chip into a thin film, thereby coating the solder balls with flux. The flux generally has an acidic component, which removes oxide barriers from the solder surfaces, and an adhesive quality, which helps to prevent the chip from moving on the packaging substrate surface during the assembly process. The flux serves primarily to aid the flow of the solder, such that the solder balls make good contact with traces on the packaging substrate. It should be understood that this electrical bonding also provides a mechanical bond between the chip and substrate.
After the flux is applied, the chip is aligned with and placed onto a placement site on the packaging substrate such that the chip""s solder balls are aligned with electrical traces on the substrate. The substrate is typically composed of a laminate or organic material, such as fiber glass, PTFE (such as Teflon(trademark), available from Gore, Eau Claire, Wis.) BT Resin, epoxy laminates or ceramic-plastic composites. Heat, for example, to a temperature of about 220xc2x0 C., is applied to one or more of the chip and the packaging substrate, causing the solder balls to reflow and form electrical connections between the chip and the packaging substrate. Then, the remaining flux residue is substantially removed in a cleaning step, for instance by washing with an appropriate solvent.
At this point, the mechanical (adhesive) bonding procedure can begin. FIGS. 1A and B illustrate the standard underfill method for mechanically bonding the chip and the substrate after the electrical connections between the chip and substrate have been made. In FIG. 1A which is a cross-sectional, side view, a chip 100 with an active circuit surface 102 has been electrically connected to a substrate surface 106 via the solder balls 104. It should be noted that this figure and the figures that follow are intended to be representative and, for example, do not show the solder balls 104 in proportion to the chip 100. As an example, the chip 100 may have dimensions on the order of 0.5xc3x970.5 inch (1 inch=2.54 cm) whereas the unbonded solder balls 104 may have a diameter on the order of 4 to 5 mils (1 mil=10xe2x88x923 inch=0.0254 mm) or less. An underfill material, typically a thermo-set epoxy 108, such as is available from Hysol Corporation of Industry, Calif. (product numbers 4511 and 4527), Ablestik Laboratories of Rancho Domingo, Calif., and Johnson Matthey Electronics of San Diego, Calif., is dispensed into the remaining space (or xe2x80x9cgapxe2x80x9d) 110 between the chip 100 and the substrate 106. In current designs, a representative gap is between 50-75 microns. In a typical procedure, a bead of thermo-set epoxy 108, is applied along one edge of the chip using an injection mechanism 112 where it is drawn under the chip 100 by capillary action until it completely fills the gap 110 between the chip 100 and the packaging substrate 106. To assist the flow, slight heating of the packaging substrate after dispensing of the underfill material 108 may be used. In some cases, the underfill material flow is further assisted by vacuum, or, alternatively, by injection of the epoxy into the gap.
To change the coefficient of thermal expansion of the underfill material, a filler material such as alumina or silica is typically added to the underfill material 108. The spots in the underfill material 108 represent a constant percentage by weight of filler material particles. The filler material, which lowers the coefficient of thermal expansion of the epoxy, increases the rigidity of the cured epoxy which increases the mechanical strength of the bond between the chip and substrate. Thus, the reliability of the packaged system is increased. However, adding filler material to the underfill material reduces the flow rate during the process by which the epoxy is drawn under the chip by capillary action. When the gap between the chip and substrate decreases, the reduced flow rate under the chip increases the possibility of the formation of gaps or voids in the underfill material which reduces the reliability of the packaged chip. An underfill material without any filler material has the best flow rate and thus produces the least amount of gaps and voids. However, using a non-filled underfill material to bond the chip and substrate leads to poor packaging reliability under temperature cycling.
In another mechanical bonding process called no-flow underfill, the underfill material 108 is placed on the package substrate underneath the center of the chip 100, before the chip 100 is electrically connected to the substrate 106. In this process, the mechanical bonding and electrical bonding occur in one step. In this process, it is undesirable to add filler material to the underfill material because the filler material adversely affects the electrical connections between the chip and the substrate. Thus, this process is limited to packaging applications where a strong mechanical bond is not required such as for small chips.
As shown in FIG. 1B, after the epoxy 108 has bled through the gap 110, a separate bead of epoxy 114 with the same composition as the underfill material is dispensed and bonded around the perimeter of the chip 100 to create a fillet 112. The fillet adds additional strength and creates a clean edge around the chip. Thereafter, the epoxy (both the underfill and perimeter bonding epoxy, if any) are cured by heating the substrate and chip to an appropriate curing temperature. In this manner the process produces a mechanically, as well as electrically, bonded semiconductor chip assembly, with the underfill material 108 allowing a redistribution of the stress at the connection between the chip 100 and the substrate 106 from the solder 104 joints only to the entire sub-chip area.
Currently, one disadvantage of the standard underfill method for filling the gap between the chip and the substrate for packaging is that as the gap size approaches 25 microns or less, which is anticipated as requirement for chips in the near future, it becomes very difficult to use underfill material with a high percentage of filler material. With small gaps approaching 25 microns, an underfill material with a high percentage of filler material produces gaps and voids in the underfill material which reduces the mechanical rigidity of the system. In addition, the voids may allow electric shorts between two adjacent solder joints. However, to reduce the gaps and voids, an underfill material with a lower percentage of filler material must be used which also reduces the mechanical rigidity of the system. Thus, a method for adding filler material into a non-filled or low filled underfill system would be desirable feature for mechanically bonding a chip to a substrate.
To achieve the foregoing, the present invention provides a semiconductor chip package with a fillet which contains a high percentage of a filler material by weight and a method of assembly with a semiconductor chip package for adding filler material to a non-filled or low-filled underfill system. The method of assembly produces a chip package where the concentration of filler material within the underfill material between the chip and the package substrate may be varied from location to location within the underfill material. The filler material increases the mechanical rigidity of the underfill material after it has hardened. Further, the filler material may help to match the coefficients of thermal expansion between the chip and the underfill material after it has hardened which reduces the mechanical stress at the interface between the underfill material and the chip. Thus, using the approach of the present invention, the percentage of filler material may be increased in regions of the underfill material where the mechanical stresses require a greater mechanical rigidity. The present invention may be applicable to increasing the reliability of chip packages where the chip and the package substrate are separated by a gap about 25-50 microns wide.
In a preferred embodiment, the present invention provides a semiconductor package including a packaging substrate having a top side and an underside and a semiconductor chip having an active surface with a center, a top surface and a perimeter. The active surface of the chip is electrically and mechanically bonded to the top side of the substrate. The semiconductor package also includes an underfill material between the chip and the substrate where the underfill material contains a percentage of filler material. Further, the semiconductor package includes a second material on top of the substrate and around the perimeter of the chip where the second material contains a higher percentage of filler material than the underfill material between the chip and the substrate. The second material on top of the substrate and around the perimeter of the chip may be used to form a fillet. Both the underfill material and the second material may be a thermo-set epoxy.
Typically, the filler material used in the semiconductor package may be alumina or silica. The percentage of filler material used in the underfill material or the second material may be varied. For example, the underfill material may contain from 0-30% filler material by weight and the second material may contain from 30-85% filler material by weight.
The concentration of filler material in the underfill material may vary from location to location within the semiconductor package to form various gradients. For example, the concentration of filler material may vary between the concentration of filler material on top of the substrate and around the perimeter of the chip and the concentration of filler material near the center of the chip. As another example, the concentration of filler material may vary between the concentration of filler material near the active surface of the chip and the concentration of filler material near the top of the package substrate.
The invention also provides a method of making a semiconductor package. The method includes providing a packaging substrate having a top side and an underside and a semiconductor chip having an active surface with a center, a perimeter, and a top surface where the active surface of the semiconductor chip is electrically bonded to electrical traces on the top side of the packing substrate. Then, an underfill material may be dispensed between the chip and the substrate where the underfill material contains a percentage of filler material. Next, a second material may be dispensed on the top of the substrate and around the perimeter of the chip where the second material contains a higher percentage of filler material than the underfill material between the chip and the substrate. Finally, the underfill material and the second material are cured. In another embodiment of the present invention, the underfill material may be dispensed prior to electrical bonding where the underfill material does not contain a filler material. Both methods may be applied for semiconductor packages where the chip and substrate are separated by a gap of about 25-50 microns.
These and other features and advantages of the present invention are described below with reference to the drawings.
FIGS. 1A-B depict cross-sectional views of stages in the packaging of a chip using a standard underfill method.
FIGS. 2A-B depict cross-sectional views of stages in the packaging of a chip using an underfill method with a highly filled fillet to add filler material to the underfill material in accordance with a preferred embodiment of the present invention.
FIGS. 3A-B depict cross-sectional views of stages in the packaging of a chip using a no flow underfill with a highly filled fillet to add filler material to the underfill material in accordance with a preferred embodiment of the present invention.
FIG. 4 depicts a cross-sectional view of a chip package with underfill material and a fillet after the curing process in accordance with preferred embodiments of the present invention.
FIG. 5 depicts a flowchart showing steps of a method for adding filler material to a non-filled or low-filled underfill material deposited using a flow underfill process using a highly filled fillet during chip packaging in accordance with a preferred embodiment of the present invention.
FIG. 6 depicts a flowchart showing steps of a method for adding filler material to a non-filled material deposited using a no flow underfill process using a highly filled fillet during chip packaging in accordance with a preferred embodiment of the present invention.